The present invention relates to a semiconductor device, and more particularly to a clock buffer circuit for buffering a clock signal.
In general, a semiconductor memory device, such as a dynamic random access memory (DRAM), comprises a memory array including a plurality of memory cells for storing data.
Particularly, in a synchronous DRAM (SDRAM) among various DRAMs, a data read/write operation is carried out synchronously with an external clock signal. For this reason, in the SDRAM, there is a need for a clock buffer circuit to generate an internal clock signal which is in synchronization with the external clock signal.
The clock buffer circuit for the SDRAM employs a differential amplifier to which a clock signal and an inverted clock signal having an opposite phase to that of the clock signal are inputted in tandem so that a clock duty ratio can be impervious to external noise.
Particularly, in semiconductor memory devices such as DDR/DDR2/DDR3 SDRAMs, data is read/written synchronously with rising and falling edges of a clock, so that it can be transmitted at a higher speed than in the existing SDRAMs.
In order to accurately synchronize data with clock edges, a clock control is required within a memory to generate an internal clock whose duty ratio to the phase of an external clock is 50:50. Also, in order to ensure an accurate output/clock phase, there is a need for a duty correction circuit (DCC) to correct a duty error of an external clock or internal clock. This DCC becomes more important in high-speed Quad Data Rate (QDR: an operation mode where four data are equally outputted during one cycle) DRAMs.
On the other hand, a conventional clock buffer circuit 100, such as a quadri coupled receiver (QCR) buffer, as shown in FIGS. 1 and 2, must be designed to generate an internal clock signal ICLK having tR (time delay from external clock rising to internal clock rising)/tF (time delay from external clock falling to internal clock falling) characteristics which are always equal in any given conditions. However, in a practical chip, the tR/tF characteristics may not be equal due to various external environmental factors, as shown in FIG. 3.
FIG. 4 illustrates variations in the tR/tF characteristics of the clock buffer circuit of FIG. 2. From this drawing, it can be seen that there is a tR/tF difference of 0.2 ns or more occurring with voltage drops (VDD variations) under the same input conditions. This means a duty distortion due to buffering, which leads to an increase in external parameters to be corrected by the DCC, resulting in a reduction in accuracy of the DCC. As a result, this duty distortion deteriorates the high-speed operation of a memory device.